The present invention is directed to binary adders and, in particular, to an improvement in the gate circuits of lookahead binary adders.
The simplest form of binary adder is the ripple-carry binary adder. It has a plurality of stages--one stage for each bit of a pair of binary numbers A and B that are to be added. Each adder stage produces two outputs: a Sum (S) and a Carry (C). The S output constitutes one of the plurality of outputs of the adder which signals the result of the addition. The C output is a carry bit, which is applied to the next-higher stage of the adder. The S output of each stage is a function of the A, B, and C inputs thereto. Whereas the A and B inputs to the adder are simultaneously available at the beginning of the add operation, the C signals are not. They ripple through successive stages of the adder, from least to most significant bit, as each stage performs its addition. The resultant delay makes ripple-carry adders relatively slow.
Lookahead binary adders improve upon the speed of ripple-carry binary adders by providing additional circuitry, dedicated to derive C signals directly from the A and B inputs. The additional circuitry comprises two main sections: a Generate/Propagate (G/P) section and a Carry-Generate (C-G) section. The G/P section itself comprises a plurality of logic circuits arranged in a series of stages, circuits in successive lookahead stages being associated with subgroups of progressively larger numbers of bits (i.e., 2, 4, 8, etc.) or adder stages. It is the function of the G/P sections to derive from the A and B inputs to the adder a set of Generate (G) and Propagate (P) signals, such G and P signals being generated for groups of 1, 2, 4, 8, etc. adder stages, up to the largest group, whose members number one-half of the total number of stages in the adder.
The other principal portion of the lookahead logic is the C-G section, which serves to derive, from the G and P signals, C signals for each stage of the adder in lieu of the C signals which would otherwise be generated by the respective adder stages themselves. As noted above, the advantage of the arrangement is that the C signals so produced can be generated much more quickly than in the ripple-carry adder.
In the G/P section of the lookahead logic, the logic circuits in the first stage receive inputs A and B from respective ones of the adder stages. Their respective outputs are expressed by the following equations: EQU G1=A.multidot.B (1) EQU P1=A+B (2)
In the second stage of the adder, the logic circuits implement the following relationships: EQU G2=G1[1]+P1[1].multidot.G1[0] (3) EQU P2=P1[1].multidot.P1[0] (4)
In equations (3) and (4), the first number after a letter reflects that the G or P term is an output from the first stage of the lookahead section. The second number after a letter (in brackets), which in the above equations is either a 1 or a 0, identifies which of the two members of the previous stage generated the term in question. It will be recalled that each such stage receives G and P outputs from two members of the previous stage of the G/P section, the less significant bit of the two being responsible for the terms identified with the [0], and the more significant bit of the two being responsible for the [1] terms of the next-higher-order section.
In the C-G section of the lookahead logic, each stage comprises logic circuits which receive as their inputs a C signal and G and P signals from a respective stage of the G/P section. Each C-G section circuit implements the relationship: EQU CO.sub.x =G.sub.x +Px.multidot.CI.sub.x ( 5)
where x is the C/P stage with which the particular C-G stage is associated.
Lookahead adders and their lookahead logic for fast-carry generation are well known, and for a more complete understanding of their operation, the reader is referred to the literature, among which is Waser et al, Introduction to Arithmetic for Digital Systems Designers, Section 3.1.3, pp. 83-88, published by Holt, Rinehart and Winston.
The logic circuits for implementing equations (1)-(5) are usually constructed of Field Effect Transistor (FET) switches having a source, a drain, and a gate. FET's, are switched, closed or open, by a signal on their gate. When switched closed, an FET provides a low-impedance current path between its source and its drain. When switched open, the FET breaks that path.
The present invention is concerned, in particular, with the presently used configuration of the logic circuits for implementing equations (3), (4), and (5). These circuits typically comprise first and second branches of series-connected FET's connected in parallel such as V.sub.SS and V.sub.DD. The circuit has an output node, and the first and second branches each comprise first and second legs (or sub-branches), the respective legs in each branch being connected between respective ones of the first and second reference potentials and the output node. Each leg of the first branch comprises first and second series-connected FET's, the first FET of each pair being connected to a respective one of the reference potentials, and the second FET of each pair being connected between the first FET of each pair and the output node. Each leg of the second branch comprises a single FET, one of which is connected between the output node and one of the reference potentials, the other of which is connected between the output node and the junction between the FET's of one of the legs in the first branch of the circuit.
The last of the above-described connections has two disadvantages. First, it is undesirable from a circuit layout standpoint. Second, it puts an FET in the second branch in parallel with one of the two series-connected FET's in the first branch. The two parallel-connected transistors are then connected in series between the node and one of the reference potentials, through the other of the series-connected first-branch FET's. In order to maintain uniform circuit speed, it is necessary that the member of the parallel-connected FET pair which is in the second branch have the same resistance as its mate in the first branch. This, in turn, implies that the two parallel-connected FET's must be of comparable size.